In the last years the memory market has been characterized by an increasing interest in high density devices and technology scaling has become more and more aggressive, both for memory core and circuitry, especially for the flash memory devices. While the technology is continuously improving to reduce the memory size, new solutions are studied to reduce the area of the related analog circuitry, which is not exclusively dependent on technology, but mainly on the specifically adopted layouts and architectures.
FIG. 1 schematically shows an exemplary structure of a memory and a memory controller of a conventional NAND flash memory.
The Flash memory 100, for example, may include page buffer, memory cell array, and configuration/redundancy data. Specific address in the Flash memory 100 can be accessed by using a Row Decoder 122 and the COLUMN Decoder 145. The ROW Decoder 122 and the COLUMN Decoder 145 are controlled by the controller that includes a ROW control system 120, a COLUMN control system 130, and a uC UNIT 140. Thereby, the data stored in the Flash memory 100 can be read to a SRAM matrix. Reversely, the data stored in the SRAM matrix can be written into a location of the Flash memory 100.
In read, write and erase operations, a voltage regulator 160 are used to produce appropriate voltages, and the voltages are supplied to the Flash memory 100.
Flash memory substantially is a non-volatile computer storage chip that can be electrically erased and reprogrammed. Generally, a Flash memory includes a lot of cells, and each cell is made, for example, by floating gate transistor. Each memory cell store the information i.e 1 if erased and 0 if programmed.
In an example when the floating gate transistor is used for each cell of a Flash memory, each memory cell resembles a standard MOSFET, except the transistor has two gates instead of one. On top, there is a control gate as in other MOS transistors, but below this there is a floating gate being insulated all around by an oxide layer. By confining or releasing electron in the floating gate, the Flash memory can thus store information for a long time without loss, due to the structure of the floating gate and control gate, i.e. the insulated floating gate. However, this specific structure for floating gate is mere an example to explain an embodiment of the invention, and does not limit the scope of the invention. Other type of transistor or memory device can be used for memory cell instead of a floating gate transistor.
To erase a cell of a Flash memory, i.e. resetting it to the “1” state, a large voltage of the opposite polarity is applied between the control gate and the source terminals or is applied between the control gate and its substrate-side well, pulling the electrons off the floating gate through quantum tunneling. This erasing operation usually can be performed on a block-wise basis, that is to say, all the cells in an erase sector are erased together.
A single-level flash cell in its default state is logically equivalent to a binary “1” value, because current will flow through the channel under application of an appropriate voltage to the control gate. In a NOR type memory, a flash cell can be programmed, or set to a binary “0” value, by applying an elevated on-voltage to the control gate terminal, causing the flowing of electrons from the source to the drain terminals, assuming an NMOS transistor. If the current between the source and drain terminals is sufficiently high, some high energy electrons could jump through the insulating layer onto the floating gate, via a process called hot-electron injection.
Generally, the program operation can be done on a byte or word basis. Alternatively, for NAND type flash memory, the program operation may be done on a page basis, whereas the erase operation is done on a block basis.
FIG. 2 schematically represents an exemplary cell matrix organization and driving circuitry of NAND memory.
The matrix of the flash memory 100 shown in FIG. 1 may include two planes shown as PLANE0 290 and PLANE 295 in FIG. 2. A PERIPHERAL CIRCUITS 210 shown in FIG. 2 includes the voltage regulator 160, the charge pumps shown in FIG. 1, and the like. A voltage regulator 215 shown in FIG. 2 corresponds to the voltage regulator 160 shown in FIG. 1.
Each of planes 290 and 295 includes a plurality of cells. The left plane of the matrix is named as PLANE0 290, and the right plane of the matrix is named as PLANE1 295. PLANE0 includes a page buffer 225, j number of row drivers 245 and j number of Blocks 240. Each of PLANE0 290, PLANE 295 includes row driver x-y where x represents row and y represents the number of plane. PLANE0 290 includes row driver 0-0, row driver 1-0, row driver 2-0, . . . row driver j-0, i.e. j row drivers. Each row driver corresponds to a block in the same row. A block is the smallest unit of the NAND array that can be erased at once. Row driver 0-0 corresponds to block 0, row driver 1-0 corresponds to block 1, and row driver j-0 corresponds to block j. Each row driver is connected to strings which belong to the corresponding block with at least one word line (unseen in FIG. 2) With regard to the detailed structure of word lines and stacks it will be described later with reference to FIG. 3.
Each of the Blocks 240 includes k number of strings 250, and each string is connected with other strings belonging to different blocks by a bit line of the same column. For example, block 0 includes S0, S1, S2, . . . Sk. Here, S represents the initial letter of “string”. Similarly, block 1 includes S0, S1, S2 . . . Sk. The other blocks, e.g. block 2, 3, . . . , block j also includes k number of strings (S0, S1, S2, . . . Sk) as well. All S0 in the blocks are connected to one another through a bit line, i.e. BL0. Here, BL is an abbreviation of bit line. In a similar manner, BL1 is connected to S1 of Block 0, Block 1, Block 2, . . . and Block j. BL k is connected to Sk in each Block 240. A Page buffer circuitry 225 of the PLANE0 290 is connected to the bit lines, such as BL0, BL1, BL2, . . . BLk, a single page buffer driving one or two bitlines.
In a similar way, the PLANE1 295 of the cell matrix is configured. PLANE1 thus includes a page buffer circuitry 230, j number of row drivers 245, j number of Blocks 240. PLANE1 295 includes row driver 0-1, row driver 1-1, row driver 2-1, . . . row driver j-1, i.e. j number of row drivers. Each row driver corresponds to a block. That is to say, row driver 0-1 corresponds to block 0, row driver 1-1 corresponds to block 1, and row driver j-1 corresponds to block j. Each row driver is connected to strings in the corresponding block with at least one word line (unseen in FIG. 2) With regard to the detailed structure of word lines and stacks, it will be described later with reference to FIG. 3.
FIG. 3 schematically represents an exemplary structure of strings, bit-lines, and word-lines.
A block 240 shown in FIG. 2 includes a predetermined number of strings 300, 301, 302, 303 shown in FIG. 3. The number of strings depends on the dimension of a page indicated in the specifications of the NAND memory device. The string 300 is composed by a predetermined number of memory cells 310 connected in series. This number depends on the process used to manufacture the NAND memory device. The string 300, 302 is connected to a bit-line BL0 through a drain-side selector cell or DST 325 and to a common source line SL through another source-side selector cell or SST 330. The gate of each cell is connected to a word line. For example, the gate of cell 311 is connected to WL1, and the gate of cell 312 is connected to WL2. The source selector cells or SST are connected to a common source line SL, thus one end of all strings is connected to the common source line SL.
A second string 301 and a fourth string 303 are coupled to a bit-line BL1, and to the common source line SL, so they also shares the common source line SL and the bit-line BL1.
Each string may be activated by controlling signals applied to the selection lines DSL and SSL. By switching the selector cells (transistors) 325, 330 on, the first string 300 can be made electrically connected to the bit-line BL0, and may pull current from it based on whether the gate of the memory cells 310, 311, 312 stores electrons or not.
To read a data stored in a specific memory cell, e.g. a memory cell 311, word lines WL0, WL2, WL3 except WL1 are controlled to be pulled up far above the threshold voltage, while the word line WL1 is controlled to be pulled up over the threshold voltage of an erased cell and below the threshold voltage of a programmed cell. SST and DST cells are switched to make inner cells to connect to the bit line BL0. Regardless of the bit stored in the memory cells 310, 312, 313, specifically a data bit stored in the floating gate of the memory cell, the memory cells 310, 312, 313 are turn into conduction by the high voltage applied thereto. For the memory cell 311, because a voltage just over the threshold voltage of an erased cell is applied to the control gate of the memory cell 311, if electrons are trapped in the floating gate of the memory cell 311, the voltage of the control gate is cancelled or partially screened by the trapped electrons, thereby the drain and source terminals of the memory cell 311 are open, and no current flows through the chain of the first string 300. Alternatively, if there-are no trapped electrons, the memory cell 311 will conduct, then current may flow through the first string 300. In this way, the current flowing from the bit-line to the source terminal or from the source terminal to the bit-line may be controlled. If the cell is erased and no electrons are trapped the cell is conductive and sensed as 1. On the contrary, a programmed cell with trapped electrons remains off state and is sensed as 0. This is an exemplary read operation of a string in the NAND flash memory.
The string structure 300 is repeated along an X-direction, which is indicated as S0, S1, . . . Sk in FIG. 2. The string structure 300 is also repeated along a Y-direction (or bit-line direction). The first and second strings 300, 301 lie in the same block, and the third and fourth strings 302, 303 lie in the same block. The DST and SST cells are controlled to select a block in the memory array.
BL0 is indicated as an even bit-line, and BL1 is indicated as an odd bit-line. Likewise, BL2, BL4, BL6, etc. can be referred to as even bit-lines, and BL3, BL5, BL7, etc. can be referred to as odd bit-lines. In a few architectures, even and odd bit-lines are selected alternatively, so that they can be read and programmed separately.
During page read and page program operations, the selected word line, the unselected word lines and the selectors gate cells, DST and SST, should be biased to a proper voltage with an established signals sequence. Word lines WL0˜WL7 and selector lines DSL0, DSL1, SSL0, SSL1 are as long as the whole array width in X direction. Moreover, the distance between a word line and another, e.g. between WL0 and WL1, is equal to the minimum technological width and this distance is only a bit lower than the distance between a selector line and an adjacent word line, e.g. between WL0 and DLS0. As a consequence, the capacitance of these lines is not negligible and should be charged and discharged by using suitable voltage sources, usually charge pumps or voltage regulators.
Moreover, the coupling parasitic capacitance between one word-line and another, e.g. between WL0 and WL1, and between selector lines and adjacent word lines, e.g. between WL0 and DLS0, can be relevant. This means that, driving a line to a proper voltage, the adjacent lines are disturbed and their voltage value tends to rise or drop, depending if the adjacent line is charged or discharged respectively. Since word lines, e.g. WL0, WL1, and selector lines, e.g. DSL0, are resistive and capacitive, a settling time is necessary to restore the correct voltage biasing on a line after it has been disturbed by adjacent lines voltage variation.
The settling time means the time required to recover the desired voltage on the line. The minimum settling time, related to the resistance and capacitance of the line, is ensured by a good driving capability of the used voltage source. In the same way, a good driving capability of the voltage source ensures the minimum rising or discharge time for the word lines and selector lines which is related to the time constant of these lines τ=*R*C where R and C are the line resistance and capacitance, respectively.
FIG. 4 schematically represents a detailed structure of the row driver 245, the switch 220, and the voltage regulator 215 of FIG. 2.
The switch 220 includes a switch driving circuitry 400 which connects one of lines Vx0, Vx1, Vx2, . . . , Vxn+1 to the voltage regulator through as example pass transistors like M1. The switch driving circuitry 400 controls the transistors like M1 to switch on or off the transistor M1. When the transistor M1 is switched on (is rendered conductive), the current flowing is produced between the voltage regulator 215 and the proper Vx line coupled to the row driver 245. Lines Vx0, Vx1, Vx2, . . . , Vxn+1 will be also referred to as Vx lines.
The row driver 245 includes a row driver driving circuitry 405 and a plurality of transistors T0, T1, . . . , Tn, Tn+1. The plurality of transistors T0, T1, . . . , Tn, Tn+1 are connected to lines Vx0, Vx1, Vx2, . . . , Vxn+1, respectively. If a user operation is requested on a page of a block, the row driver driving circuitry 405 controls the plurality of transistors T0, T1, . . . , Tn, Tn+1 to deliver correct biasing from Vx lines to each of the word lines WL0˜WLk and gate selector lines SSL, DSL. Vx lines are as long as the whole matrix in Y direction, since they connect all the row drivers. These lines are usually designed with metal connection and ensure low resistivity. Their capacitance, instead, can be high due to the line length. Moreover, Vx lines are designed in parallel and often capacitively coupled one to another. Vx lines receive their biasing through switches 220 which connect the output of voltage regulators (as 215 in the picture) to Vx lines. One voltage regulator can be connected to a single Vx line or more, depending on the required voltages and sequences.
In FIG. 4, it is shown that only one voltage regulator 215 to provide a bias voltage. However a plurality of voltage regulators can be used, each of the voltage regulators being connected to a different Vx line ore more than one Vx line.
To read data stored at a specific address at a certain point of time, the block storing the data should be firstly identified, then an exact word line in the block should be chosen. This operation can be performed by the row control system 120 and the row decoder 122 in FIG. 1. Then, based on the result of the row decoder 122, source selector line SSL, drain selector line DSL, selected word line, and unselected word line are identified. For example, if it is assumed to choose a word line WL1 in FIG. 4 after an address decoding, the DSL and SSL lines of the same block are driven by the row driver to switch on the corresponding transistor. The lines except WL1, i.e. WL0, WL2, WL3, . . . , WLk are driven by the row driver to have a specific bias voltage which is different from the bias voltage for WL1. In short, the unselected word lines, i.e. WL0, WL2, WL3, . . . , WLk, should be correctly biased even if it is not addressed in a user mode operation as read or program. In fact, as it is well known, erase operation involves the whole block which is globally addressed, while in read and program operations the user selects a word line by addressing it, also the other word lines of the same block and the related selectors having to be correctly biased.
When the output of the voltage regulator 215 is delivered to the word line or the selector line, the switch driving circuitry 400 is enabled and rises the pass gate voltage, i.e. the voltage value which enables the pass gate transistors. Also, the row driver 245 is enabled and connects in a similar way the Vx lines to a desired word line or selected gate line. The voltage regulators 215 charge not only the word line WL0˜WLk and the selector lines SSL, DSL but also the VX lines connecting the row driver 245 to the switch 220.
FIG. 5A schematically shows a voltage regulator 501 being realized according to the prior art and being used for biasing a word line.
The voltage regulator 501 shown in FIG. 5A corresponds to the voltage regulator denoted by 160 in FIG. 1 or by 215 in FIGS. 2 and 4.
The voltage regulator 501 includes a two stage operational amplifier 500. The two stage operational amplifier 500 includes a first stage comprising an operational amplifier OP1 and a second stage including transistors M1, M2. Preferably, the second stage may be further coupled to capacitors C1, C2. The voltage regulator 501 further includes a transistor M3 connected as a follower configuration, and a divider R1. The divider R1 divides the regulator output voltage provide at the regulator output OUT and provides a feedback signal Vfeed to the non inverting input + of the OP1, which is the inverting input of the voltage regulator as a whole, since the transistor M2 acts as an inverting stage. In particular, it should be remarked that the second stage is an inverting stage so the positive input of the first stage is the inverting input of the regulator. The feedback is always provided to the inverting input of the voltage regulator. In the second stage, a first transistor M1 works as a current reference and a current mirror. In particular, the first transistor M1 is able to replicate on its drain terminal the same current of a current generator, multiplied by a constant factor. A specific structure of the voltage regulator 501 is shown in FIG. 5B.
An output signal at an output terminal OUTa of the first stage of the two stage operational amplifier 500 is amplified by a second transistor M2 of the second stage. A further output signal at an output terminal OUTb of the second stage of the two stage operational amplifier 500 is provided to the gate of the transistor M3 in follower configuration.
The output terminal OUT of the voltage regulator 501 provides an output voltage Vout being substantially a constant voltage to other circuitry. Such an output voltage Vout is determined based on a reference voltage Vref provided to the non inverting terminal of the operational amplifier and the resistance ratio of the divider R1. A feedback signal Vfeed at the non-inverting input (+) of the operational amplifier OP1 of the first stage is determined by the dividing ratio (a:b) of the divider R1, according to following formula:
  Vfeed  =            a              a        +        b              ⁢    Vout  
The operational amplifier OP1 of the first stage compares two inputs, i.e. the reference voltage Vref and the feedback signal Vfeed, and when there is a slight change of the value of the feedback signal Vfeed, the output voltage at the output terminal OUTa of the first stage changes to adjust the output voltage Vout to a specific value. This is called negative feedback. Due to the negative feedback configuration, the output voltage Vout remains stable and constant.
In this way, when the reference voltage Vref is fixed and the dividing ratio (a:b) of the divider R1 is fixed, the output voltage Vout is regulated, controlled or produced by the voltage regulator 501 so as to be constant.
On the other hand, the output voltage Vout is varied as follows. The dividing ratio (a:b) of the divider R1 may be digitally controlled by a control signal. By changing the dividing ratio (a:b) of the divider R1, it is possible to change the output voltage Vout of the output terminal OUT of the voltage regulator 501. Alternatively, the reference voltage Vref may be changed in order to control the output voltage Vout. Hence, by changing such parameters as the dividing ratio (a:b) and/or the reference voltage Vref, the output voltage Vout can be changed from a high voltage level to a low voltage level for example, from Va (5 V) to Vb (2.5 V).
FIG. 5B shows an exemplary circuit structure of the voltage regulator of FIG. 5A. The dot-block denoted by OP1 shown in FIG. 5B corresponds to the OP1 shown in the two stage operational amplifier 500 in FIG. 5A. The current mirror blocks 510 and 520 are newly shown here in FIG. 5b, which are omitted to be shown in FIG. 5 A for simplicity.
The operational amplifier OP1 of FIG. 5A has a differential amplifier configuration. In particular, such an amplifier includes five transistors M5, M6, M7, M8, M9. The gate terminals of the transistors M5 and M6 are coupled to each other. The drain and gate terminals of the transistor M5 are connected with each other. The differential input voltage values, Vfeed and Vref, are provided to the transistors M7 and M8. In particular, the feedback signal Vfeed is provided to the gate terminal of the transistor M7, and the inverting input voltage, i.e. the reference voltage Vref, is provided to the gate terminal of the transistor M8. The output voltage at the output terminal OUTa of the first stage is generated at the connection of the transistors M6 and M8. The gate terminal of the transistor M9 is provided with a bias voltage from a current mirror block 510. The transistor M9 thus provides a constant current into the first stage, in particular to the operational amplifier OP1, due to the current mirror block 510.
The current mirror block 510 is realized by an improved Wilson current mirror to reduce the channel length modulation effect on the p-MOS transistors M9, M10, M11, M12, which could cause a mismatch on the current mirrored for the operational amplifier OP1 of the first stage and the second stage, i.e. the transistor M1, of the two stage operational amplifier 500.
The transistors M13 and M14 replicate a current Isrc being provided by a current source and flowing through the transistor M14 to the drain and source terminals of the transistor M13. The amount of the current as replicated depends on the ratio of channel width of both transistors M13 and M14, being the length of M13 and M14 are always the same. Same amount of the replicated current on the transistor M13 flows through the transistors M10 and M12.
The transistor M12 is coupled with the transistor M11 and the transistor M1 for realizing a current mirror configuration. For example, it is assumed that a current I is flowing through the transistor M12, the mirroring factor for the transistor M11 is N, and the mirroring factor for the transistor M1 is M. Then, the current I is mirrored and multiplied by a factor N to bias the operational amplifier OP1 of the first stage. Similarly, the current I is mirrored and multiplied by a factor M to bias the second stage, specifically the transistor M1.
The current Idiv flowing through the divider R1 is dependent on the output voltage Vout of the output terminal OUT and the total resistance value of the divider R1. Under the hypothesis that no current consumption is present to the external load coupled with the output terminal OUT, the current Idiv flows inside the transistor M3. In this case, the total power consumption of the voltage regulator 501 is as follows:
      I    +          N      ·      I        +          M      ·      I        +          I      div        =                    (                  M          +          N          +          1                )            ·      I        +                  V        out                    R        ⁢                                  ⁢        1            
All these parameters are established during the design phase and they should be thus under control.
In FIG. 5B, a current flow indicted as Iout is shown. The current flow is produced in a charging phase. To charge the Vout node is needed in several cases such as during a rising transient or when a sudden drop of the output voltage Vout occurs. In the charging phase, a high current is sunk from the output terminal OUT to the external load, and the follower, i.e. the transistor M3, is able to provide a very high current. This charge is accomplished by the current flow indicted as Iout in FIG. 5B.
The sizing of the transistor M3 may be chosen appropriately to charge an external capacitive load in a short time. The current Iout should be high enough to charge the word lines or selector line of FIG. 4 within a proper time. This fast charge can be carried out by the transistor M3, so this circuit configuration works well when it needs to charge the load into a specific voltage or when there is a sudden voltage drop.
In FIG. 5B, another current flow indicated as Idis is shown. The current flow is produced in a discharging phase. To discharge the Vout node is needed in several cases such as when the output voltage Vout happens to be higher than the desired voltage, when a coupling effect as raising the output line for example word line or gate selector line occurs and the output line is needed to be decreased from its raise, when a sudden surge of the output voltage Vout occurs, when the external capacitive load is required to be discharged to adjust the output voltage Vout to a lower desired voltage, or when a bias voltage of the output line (i.e. word line or gate selector line) coupled to the Vout node of the voltage regulator changes from a high voltage level to a low voltage level, for example from Va (5 V) to Vb (2.5 V). The discharge is accomplished by the only current flow indicted as Idis in FIG. 5B.
However, in the discharging phase, a long time is needed to discharge the external capacitive load (i.e. the Vout node of the voltage regulator) through the divider R1, where a discharge current Idis flows through the divider R1 itself to the ground. The discharge current Idis is inevitably small since the resistance value of the divider R1 should be high in order to limit the DC power consumption occurring at the divider R1. For instance, the discharge current Idis should be few μA or tens of μA. To discharge the Vout node as explained above is accomplished because of the only discharge path indicated by Idis, and thus another discharge path discharging the Vout node, which is differently from this discharge path, is not provided.
Therefore, the technical problem of the voltage regulator according to the prior art lies in that the speed of discharging in the discharge phase is not fast, which degrades the performance of a NAND flash memory.